What is a Transistor and How Does it Work? (2026 Guide)

A transistor is a three-terminal semiconductor device that uses a small voltage at one terminal to control a much larger current flowing between the other two. That’s the textbook definition. The practical reality is that the transistor is the most consequential invention of the 20th century. Without it, no computers, no smartphones, no internet, no AI, no GPS, no electric cars. Apple’s M4 chip packs roughly 28 billion transistors into a die smaller than a postage stamp. NVIDIA’s Blackwell B200 GPU has 208 billion. Each one of those is the same fundamental device that Bell Labs built out of a bent paper clip and a slab of germanium in December 1947.

This guide explains what a transistor is, how it actually works, the major types you’ll encounter from BJT to GAAFET, and where the technology sits in 2026 as Moore’s Law decelerates and the industry pushes into 2nm and beyond. The physics is genuinely beautiful and the engineering is genuinely insane, and most explanations bury both behind metaphors that don’t survive a second read. I’ve kept the metaphors where they help and dropped them where they don’t.

What is a transistor?

A transistor is a semiconductor device with three terminals. A small electrical signal applied to one terminal — the gate (in field-effect transistors) or base (in bipolar transistors) — controls whether current flows between the other two terminals. That control is the entire point. With a transistor you can build a switch (current is allowed or blocked), an amplifier (a small input signal modulates a much larger output current), or a logic gate (multiple transistors combine to compute AND, OR, NOT, NAND, NOR).

The “semiconductor” part is the key word. Transistors are made from materials like silicon and germanium that conduct electricity under some conditions and block it under others. The “doping” process — adding tiny, controlled amounts of impurities like phosphorus or boron — creates regions of the silicon with extra electrons (n-type) or extra “holes” where electrons should be (p-type). The interfaces between n-type and p-type regions are where the magic happens. Apply a voltage, the carriers redistribute, and a channel either forms or doesn’t. That’s a transistor.

The word itself is a portmanteau of “transfer resistor” — the device transfers a signal across a resistive junction. John Pierce of Bell Labs coined the term in May 1948 after the team had built the first working unit but before they had named it. The name stuck because it described what the device did: it transferred a small input through a resistive barrier to produce a controlled larger output.

History: how the transistor was actually invented

December 16, 1947, at Bell Labs in Murray Hill, New Jersey. John Bardeen, Walter Brattain, and William Shockley demonstrated the first working point-contact transistor. The device was crude — a strip of gold foil pressed onto a chunk of germanium with a paper clip bent to maintain contact. It amplified a signal by a factor of 100. The team had been searching for a solid-state replacement for the vacuum tube for years. Vacuum tubes were the pre-transistor switching technology: hot, fragile, power-hungry, and large. The transistor was small, cool, durable, and used a fraction of the power.

The 1956 Nobel Prize in Physics went to all three. Shockley took most of the credit publicly, which led to the team breaking up and Shockley founding his own company in California in 1956. The “traitorous eight” — eight engineers including Robert Noyce and Gordon Moore — left Shockley Semiconductor in 1957 to found Fairchild Semiconductor. Noyce and Moore later left Fairchild to found Intel in 1968. The entire modern semiconductor industry is downstream of one bent paper clip in a Bell Labs lab and the personality conflicts that followed.

The point-contact design didn’t last. Shockley’s junction transistor (1948) was more reliable. The bipolar junction transistor (BJT) became the dominant design through the 1960s. The metal-oxide-semiconductor field-effect transistor (MOSFET) was patented in 1959 by Mohamed Atalla and Dawon Kahng at Bell Labs and became the dominant design from the 1970s onward, when integrated circuit fabrication caught up to its requirements. Every CPU you’ve ever owned uses MOSFET-derived transistors.

How does a transistor actually work?

Take a MOSFET, the type that powers your laptop. Three terminals: source, gate, drain. Underneath the gate sits a thin layer of insulator (silicon dioxide, the “oxide” in MOSFET) and beneath that is a region of semiconductor between the source and drain. With no voltage on the gate, this region is doped p-type — it has plenty of holes but no free electrons. The source and drain regions are doped n-type with plenty of electrons. The two n-type regions can’t conduct to each other through the p-type bulk because there’s a depletion region (a barrier) at each junction blocking the flow.

Apply a positive voltage to the gate. The electric field from the gate (transmitted through the thin oxide insulator without any current actually flowing through the gate itself) pulls electrons in the p-type semiconductor up toward the surface. At a high enough gate voltage, called the threshold voltage, so many electrons accumulate at the surface that the region right under the gate inverts from p-type to effectively n-type. A conducting channel of electrons now connects the source and drain. Current flows. The transistor is “on.” Lower the gate voltage below threshold and the channel disappears. Current stops. The transistor is “off.”

What’s beautiful about this: the gate uses essentially zero current. The control signal is a voltage, not a current. That means you can run billions of transistors with much less power than billions of bipolar transistors would require — which is why MOSFET-based CMOS logic dominates digital circuits.

What’s quietly broken at modern scales: at 3nm and below, the gate is so thin that quantum tunneling lets electrons leak through the oxide even when the transistor is “off.” Leakage current is what limits how many transistors can be packed into a given thermal budget. The newest transistor designs (FinFET, GAAFET) are largely engineering responses to leakage problems that don’t exist at the larger geometries of 1990s chips.

Types of transistors: BJT, MOSFET, FinFET, GAAFET

Bipolar Junction Transistor (BJT) — 1947

The original. Three layers of doped semiconductor in a sandwich: NPN (the standard) or PNP (the inverse). Current flows when a small base current is injected, allowing a much larger collector-emitter current. Current-controlled rather than voltage-controlled. Still widely used in audio amplifiers, RF circuits, and analog signal processing where current gain matters more than power efficiency.

What’s good: high current gain (typically 100-1000x), reliable analog behavior, simple physics. What’s broken at scale: the base current draws real power, so a million BJTs running simultaneously would cook anything you packed them into. Where they live in 2026: guitar amps, radio receivers, sensor amplifiers, and the input stages of high-end DACs.

Metal-Oxide-Semiconductor FET (MOSFET) — 1959

The transistor that built modern computing. Voltage-controlled (the gate sits over an insulating oxide), so it draws negligible static current. NMOS uses electrons as carriers, PMOS uses holes. CMOS combines both in pairs to build logic gates that consume power only when switching. Every microprocessor from the Intel 4004 (1971) onward uses MOSFET-derived transistors.

What’s good: scales beautifully, low static power, high density. What’s broken below 22nm: short-channel effects start dominating. The gate can’t control the channel cleanly when the channel is shorter than the depletion regions, and leakage current spikes. Planar MOSFET stopped scaling effectively around 22nm and the industry needed a new structure.

FinFET — 2011

3D structure where the channel is formed as a vertical “fin” of silicon, and the gate wraps around three sides of it. Solved the planar MOSFET leakage problem by giving the gate more control over the channel. Intel’s 22nm Tri-Gate (2011) was the first commercial FinFET. TSMC and Samsung followed at 16nm. Every chip from 22nm down to 5nm used FinFET geometry.

What’s good: dramatically better leakage characteristics than planar MOSFET, enabled scaling to 5nm. What’s broken at 3nm: even three-sided gate control isn’t enough as the fins get thinner. Variability in fin width across millions of transistors causes performance scatter that limits clock speeds.

Gate-All-Around FET (GAAFET) — 2022

The current state of the art. The channel is a stack of horizontal silicon nanosheets, and the gate wraps all four sides of each sheet. Maximum gate control, minimum leakage. Samsung was first to ship at 3nm in June 2022. TSMC’s N2 (2nm, 2025) uses GAAFET geometry. Apple Silicon M-series chips from M5 onward will likely run on GAAFET-based silicon.

What’s good: best gate control geometry physics allows. Multiple nanosheet stacks per device, so you tune drive current by varying the number of sheets. What’s broken: manufacturing complexity is enormous. Yield rates at 2nm GAAFET are reportedly half of mature FinFET yields. Cost per transistor is rising for the first time in computing history.

CFET (Complementary FET) — research, post-2030

The next geometry. NMOS and PMOS transistors stacked vertically in the same footprint instead of side-by-side. Halves the area cost of CMOS logic. Imec demonstrated functional CFET in research conditions in 2024. Commercial production targets the 2030+ timeframe at sub-1nm process nodes.

What’s good: the only known geometry that gets density gains beyond GAAFET without exotic materials. What’s broken: manufacturing CFET requires layer-transfer techniques that don’t exist at production volumes yet. Chip designers are already preparing tooling on the assumption that CFET is what comes after 2nm GAAFET, but the schedule is genuinely uncertain.

Where transistors actually live in 2026

Transistor count per device, current generation, gives a sense of how absurdly far the technology has come from that 1947 paper-clip prototype:

• NVIDIA Blackwell B200 (AI accelerator): 208 billion transistors. The largest commercial chip ever shipped.
• Apple M4 Max (laptop CPU/GPU): ~28 billion transistors at 3nm.
• AMD Ryzen 9 9950X (desktop CPU): ~12.5 billion transistors at 4nm.
• iPhone 17 Pro (A19 Pro): ~21 billion transistors at 2nm GAAFET (TSMC N2).
• 1971 Intel 4004 (first commercial CPU): 2,300 transistors. The whole chip.

Beyond CPUs and GPUs, transistors define every digital device: smartphones (the SoC plus discrete components for power management, modem, audio), cars (modern vehicles ship with 1,000+ ICs), aircraft, satellites, medical devices, smart appliances, hearing aids, even modern toasters. Power MOSFETs handle the high-current switching in EV inverters and solar microinverters. RF transistors (often gallium nitride or gallium arsenide rather than silicon) drive cellular base stations and 5G antennas.

Analog applications survive too. Audio amplification, sensor signal conditioning, voltage regulation, motor control — anywhere the precise relationship between input and output signal matters more than digital switching speed. The bipolar junction transistor that started everything in 1947 is still in active production for these jobs.

Moore’s Law and what comes next

Gordon Moore’s 1965 observation — transistor count per chip doubles roughly every two years — held with remarkable consistency for five decades. From 2,300 transistors on the Intel 4004 in 1971 to ~3 billion on a desktop CPU by 2010, the doubling rhythm was visible. After 2015, the rhythm slowed. The economic version of Moore’s Law (cost per transistor halves every two years) effectively ended around the 28nm node — costs have been roughly flat per transistor since, and at 2nm GAAFET they’re rising for the first time.

Three things drive the slowdown. Physics: the gate oxide is getting thin enough that quantum tunneling matters. Economics: a leading-edge fab now costs $20 billion+ to build, which only TSMC, Samsung, and Intel can afford. Variability: at 3nm and below, atomic-level manufacturing variation causes chips to differ from each other in ways that affect yield and binning.

What comes next isn’t more shrinking — it’s stacking. 3D chip architectures, where multiple silicon dies are bonded vertically with through-silicon vias, are the path forward. AMD’s V-Cache stacks SRAM atop CPU dies. Apple’s M-series uses unified memory architectures that put RAM on the same package. NVIDIA’s CoWoS packaging stacks HBM memory next to GPU compute. The transistor itself isn’t getting much smaller after 2nm GAAFET; the silicon is going up instead of down.

Beyond silicon, gallium nitride (GaN) transistors are taking over high-power switching applications (EV chargers, server PSUs, RF) where their wider bandgap allows higher voltages and faster switching than silicon. Silicon carbide (SiC) handles even higher power densities in industrial inverters and EV traction. These won’t replace silicon in CPUs anytime soon — they’re more expensive and the manufacturing infrastructure is decades behind silicon — but for specialty applications they’re already the better choice.

Why understanding transistors matters

You don’t need to know transistor physics to use a computer. Most people don’t and that’s fine. But if you want to understand why your phone gets warm during long video calls, why GPUs cost what they do, why TSMC is geopolitically central to the AI race, why the M4 MacBook Air outperforms the i7 desktop you bought in 2018 — those answers all sit on top of transistor physics. The economic and geopolitical contests of the next decade are downstream of who can manufacture the smallest, most reliable transistors at scale.

For students and engineers: transistors remain the single most important concept in electronics education. Every digital design course assumes you understand them. Every embedded systems project will eventually hit a problem solvable with the right MOSFET. The 1947 invention that started this is still the foundation underneath everything we build with electricity in 2026, and probably for the rest of this century.

For more on the physics underlying transistor operation, see macrostates, microstates, and thermodynamics for the statistical mechanics that govern carrier behavior. If you’re learning electronics from scratch, the best physics textbooks for college guide and best physics YouTube channels roundup point you at the resources I’d actually recommend. For exam prep specifically, revise physics for JEE Main covers the engineering-entrance angle.

Building circuits with transistors: a practical primer

If you want to actually use transistors rather than just understand them, the entry point is a discrete BJT or MOSFET on a breadboard. Buy a starter pack from any electronics supplier (Adafruit, SparkFun, or Mouser will all sell you a hundred 2N3904 NPN transistors for under $10) and build the canonical first circuit: an LED switched on by a button press, with the transistor amplifying the tiny button current to drive the much larger LED current. Total parts cost: under $5. Total time: 30 minutes. The conceptual leap from “I know what a transistor is” to “I can use one” happens during that build.

From there, the next step up is logic gates. Two N-channel MOSFETs and a pull-up resistor build a NAND gate. Six transistors plus three resistors give you a full inverter pair. The conceptual jump from “I built a NAND gate” to “I understand how a CPU works” is real but requires a few thousand more transistors than fit on a breadboard. That’s where simulators come in. LTspice (free from Analog Devices) and CircuitJS (free, browser-based) let you simulate transistor circuits with arbitrary complexity. Drop in a model, set the bias, run a transient analysis, and you can see what the actual signals look like at every node.

For embedded systems work, you’ll mostly use transistors as level shifters, motor drivers, and signal isolators rather than as raw switches. The MCU does the logic; the transistors handle the power. A common pattern: a 3.3V GPIO pin drives an N-channel MOSFET gate, the MOSFET switches a 12V motor or a 24V solenoid, and the load doesn’t care that the controller runs on 3.3V. This pattern repeats in every robotics project, every IoT device, every consumer gadget. Knowing which MOSFET to pick (the on-resistance, the gate threshold, the drain current rating, the package thermal) is most of practical electronics in 2026.